Computer Systems: A Programmer's Perspective (3rd Edition)
Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
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Chapter 11.3, Problem 11.1PP
Program Plan Intro

IP addresses:

  • The IP address denotes an unsigned integer that is 32-bit.
  • The IP addresses is been stored by network programs in IP address structure.
  • The addresses present in IP address structure are stored in network byte order.
  •  An unsigned 32-bit integer is converted from host byte order to network byte order by “htonl” function.
  • An unsigned 32-bit integer is converted from network byte order host byte order by “ntohl” function.
  • The IP address is presented to humans in a form known as “dotted-decimal” notation.
    • Each byte is been represented by its corresponding decimal value and is separated by a period from other bytes.

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3- What is the difference between: a- MOV BX,[1234H] and LEA BX,[1234H] b- LDS AX,[200H] and LES AXX,[200H] 4-Use MOV to load address of memory MEM1.
Problem Question 03 (CO3) [0.5 + 0.5 = 1]: Given below are the contents of several Intel 8086 registers and PHYSICAL memory addresses (ALL in hexadecimal): Registers: Memory Locations [Physical Address] = Contents [05000] = 3300 [06000] = 4444 [07000] = 5555 [95000] = 367A [96000] = 6666 [97000] = 10C5 DI = 3000 %3D BX = 3000 %3D ВР 3 С345 For the following instructions, determine the contents of AX after the each of the instruction has been executed: (а) MOV (b) MOV АХ, ВР АХ, [ВХ+DI] AX = AX
(c) The following Sigma 16 program has been loaded into memory at address 0000: load R3,y[RO] load R4,x[RO] lea R5, 2[RO] sub R1,R4,R3 mul R2,R1,R5 store R2,w[RO] trap RO,RO,RO x data 10 y data 12 w data 0 Show the content of the memory writing hexadecimal representation and using a table with 3 columns: the memory address, the contents of that memory address, and an explanation of what "the content (of that memory address) means". As a reference, here are the opcodes for RRR instructions: add 0, sub 1, mul 2, trap c. And here the opcodes for RX instructions: lea 0, load 1, store 2. [7]
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